The PCI bridge can do read/write with up to 4 PCI data phases. On a write with more then 1 data phase, would the 68000 need to write to the data registers in the PCI bridge 4 times? Or does the bridge just write to the PCI slave 4 times with the same data in the data registers?

If we are to update the data register in the PCI bridge, how do we sychronize 68000, the PCI bridge and the PCI slave? Can we assert /DTACK until the data transfer begins between the PCI bridge and PCI slave?

-- Angus Cheung (cheungs@ecf.toronto.edu), March 13, 1999

Answers

Like the DMA lab, the data registers on both sides (PCI master and slave) hold the *last* data item. (You always write into the same place.) However on the slave side we have the trace FIFOs which store each data item separately. Of course since the source in this case is the bridge's data register, all the data will be the same anyway. It is a fairly simple modification to get the bridge as master to vary the data in some way on a PCI write, so this would be a useful feature to add for testing.

Robin

-- Robin Grindley (grindley@eecg.toronto.edu), March 14, 1999.